High-speed and low-voltage driven analog-to-digital converter

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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Details

341158, 341118, 341120, H03M 138

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active

056776926

ABSTRACT:
An N-bit A/D converter comprises 2.sup.N cells connected in cascade, wherein the start cell receives an input analog signal and each cell performs a determination operation to produce a determination signal. Each cell comprises a sample and hold circuit, a comparator, and a subtracter. The sample and hold circuit samples an analog value from a first analog signal received from a previous cell and holds the analog value. The comparator compares the analog value with a reference value to produce the determination signal. The subtracter subtracts a subtrahend value from the analog value to produce a second analog signal which is received by a next cell. The next cell receives the output of the cell as the above-mentioned first analog signal and performs the same determination operation as the cell. The cascade-connected cells are controlled with timing clocks so as to perform a pipeline operation such that the cell produces the determination signal when the next cell receives the second analog signal.

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patent: 5489904 (1996-02-01), Hadidi
patent: 5499027 (1996-03-01), Karanicolas et al.
T. Kumamoto et al.; "An 8-bit High-Speed CMOS A/D Converter"; IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, Dec. 1986, pp. 976-982.
S.H. Lewis; "Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications"; IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 39, No. 8, Aug. 1992, pp. 516-523.
D.G. Nairn et al.; "Algorithmic analogue-to-digital convertors using current-mode techniques"; IEE Proceedings, vol. 137, Pt. G, No. 2, Apr. 1990, pp. 163-168.
D. Macq; "A 10-Bit Pipelined Switched-Circuit A/D Converter"; IEEE Journal of Solid-State Circuits, vo. 29, No. 8, Aug. 1994, pp. 967-971.

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