Excavating
Patent
1994-01-25
1995-09-26
Voeltz, Emanuel T.
Excavating
324 731, G06F 1100, G01R 3128
Patent
active
054539935
ABSTRACT:
Disclosed is a semiconductor integrated circuit which can be tested with a high-speed clock of actual operation level or more, even if a relatively low-priced IC tester which is not capable of supplying high-speed clocks is employed, and a method of testing the same. An exclusive OR gate (2) of the semiconductor integrated circuit receives the first test clock (TCLK1) through the first test clock input pin (P1) into the first input and the second test clock (TCLK2) through the second test clock input pin (P2) into the second input, to output a high-speed clock (SCLK) resulting from the test clocks to an A input of a selector (3). Thus, the semiconductor interacted circuit internally generates the high-speed clock having higher frequency than that of the test clock to operate an internal circuit, thereby being tested with clock frequency of actual operation level or more even by means of the relatively low-priced IC tester.
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Kitaguchi Akira
Taniguchi Masaharu
Mitsubishi Denki & Kabushiki Kaisha
Tran Alan
Voeltz Emanuel T.
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