DCT peripheral for a digital signal processor

Details DCT peripheral for a digital signal processor DCT peripheral for a digital signal processor

1994-06-10

1995-09-26

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

054539463

ABSTRACT:
A discrete cosine transform engine is disclosed. The engine receives an input matrix of data and provides a transformed matrix of data, the input matrix and the output matrix each having a plurality of row locations and a plurality of column locations. The engine includes a plurality of input accumulators and a plurality of output accumulators. The plurality of input accumulators accumulate data from the input matrix of data in parallel to provide a plurality of transform coefficient outputs. A digital signal processor receives the plurality of transform coefficients, multiplies the transform coefficients by a plurality of transform constants and provides a plurality of transform products. Each output accumulator receives the transform products and accumulates the products to provide the transformed matrix of data.

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Paul M. Embree et al, "C Language Algorithms for Digital Signal Processing", Chapter 7, pp. 356-367, undated.
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IEEE Micro Chips, Systems, Software, and Applications, "A 160-Mpixel/s IDCT Processor for HDTV", Oct., 1992, pp. 28-32.

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