Method of fabricating FET device with narrow gate length

Details Method of fabricating FET device with narrow gate length Method of fabricating FET device with narrow gate length

1996-09-11

1997-10-14

Tsai, Jey

Fishing, trapping, and vermin destroying

437186, H01L 21265

Patent

active

056772181

ABSTRACT:
The present invention relates to a method of forming a local threshold voltage ion implantation to reduce the junction capacitance in a semiconductor device. A polysilicon layer is formed over the device. A first dielectric layer is formed on the polysilicon layer. Then an opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a second dielectric layer is formed on the first dielectric layer. An etching step is used to formed sidewall spacers on the inner sidewalls of the opening. Then an ion implantation is performed by using said first dielectric layer and sidewall spacers as a mask.

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patent: 5534447 (1996-07-01), Hong
patent: 5538913 (1996-07-01), Hong
Ghandhi, "VLSI Fabrication Principles Silicon and Gallium Arsenide", p. 524, John Wiley and Sons 1983.

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