Process of fabricating dynamic random access memory cell

Details Process of fabricating dynamic random access memory cell Process of fabricating dynamic random access memory cell

1990-01-22

1991-01-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 60, 437228, 437235, 437918, 437981, 357 236, H01L 2170

Patent

active

049870912

ABSTRACT:
For making an inter-level insulating film between a capacitor electrode and a gate electrode mild at the shoulder portion thereof, a doped polysilicon film is overlain by a silicon oxide film on a dielectric film structure, and the silicon oxide film is slightly etched through an isotropical technique by using a mask layer for forming a hollow space with a generally quarter-circle configuration beneath the mask layer, then anisotropically etching the silicon oxide and the doped polysilicon by using the same mask layer, then depositing silicon oxide on the entire surface, then exposing the surface of a semiconductor substrate by using an etch-back technique for leaving the inter-level insulating film on the capacitor electrode, then forming a gate electrode on the inter-level insulating film. Since a declining shoulder portion takes place at the upper end of the silicon oxide film due to the isotropical etching, the inter-level insulating film and, accordingly, the gate electrode smoothly extend over the capacitor electrode, and, for this reason, the gate electrode is free from undesirable disconnection.

REFERENCES:
patent: 4112575 (1978-09-01), Fu et al.
patent: 4164751 (1979-08-01), Tasch, Jr.
patent: 4350536 (1982-09-01), Nakano et al.
patent: 4409722 (1983-10-01), Dockerty et al.
patent: 4711699 (1987-12-01), Amano
patent: 4918503 (1990-04-01), Okuyama

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