Semiconductor integrated circuit having MOS memory and bipolar p

Details Semiconductor integrated circuit having MOS memory and bipolar p Semiconductor integrated circuit having MOS memory and bipolar p

1994-12-20

1995-09-26

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257903, 257904, 257377, 257382, 257384, 257383, 257515, H01L 2906, H01L 2711, H01L 2704

Patent

active

054536405

ABSTRACT:
In a semiconductor integrated circuit having a block of static memory cells using CMOS transistors and peripheral components using bipolar transistors, metal interconnections in a layer over the CMOS transistors on the substrate are simplified by using buried layers in the substrate as supply and ground lines for the CMOS transistors. This is accomplished by making buried contacts of a metal such as tungsten in each memory cell to make ohmic connection of the diffused layer of n-MOS transistors and the diffused layer of p-MOS transistors respectively to underlying buried layers of opposite conductivities and applying supply voltage or ground potential to each buried layer from the substrate surface by using additional buried contacts which are made at convenient locations outside the memory block. In the case of n-MOS memory cells using resistors or TFTs as load elements, ground potential is applied to the n-MOS transistors by the same method.

REFERENCES:
patent: 4503451 (1985-03-01), Lund et al.
patent: 4933739 (1990-06-01), Harari
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 5252845 (1993-10-01), Kim et al.
patent: 5350934 (1994-09-01), Matsuda
patent: 5357132 (1994-10-01), Turner
patent: 5386131 (1995-01-01), Sato

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