Sub-micron diffusion area isolation with SI-SEG for a DRAM array

Details Sub-micron diffusion area isolation with SI-SEG for a DRAM array Sub-micron diffusion area isolation with SI-SEG for a DRAM array

1994-05-31

1995-09-26

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437 89, H01L 2176, H01L 21336

Patent

active

054533961

ABSTRACT:
The present invention is a process for forming diffusion areas and field isolation regions on a silicon substrate, by the steps of: growing a field oxide layer on the surface of the substrate; forming a mask pattern which exposes a plurality of spaced-apart regions on the surface of the field oxide layer; removing portions of the field oxide layer in the exposed, spaced-apart regions with an anisotropic etch so as to leave a cavity in each spaced-apart region, each cavity having as its floor an exposed region of the silicon substrate, and having vertical walls of field oxide; angularly chamfering the rim of each cavity with a facet etch; and filling each cavity with silicon using selective epitaxial growth, and using the floor of each cavity as the seed crystal for such growth.

REFERENCES:
patent: 5100830 (1992-03-01), Morita
patent: 5135884 (1992-08-01), Miller

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