Method for manufacturing a contactless floating gate transistor

Details Method for manufacturing a contactless floating gate transistor Method for manufacturing a contactless floating gate transistor

1993-05-25

1995-09-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 4852, H01L 218247

Patent

active

054533910

ABSTRACT:
An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

REFERENCES:
patent: 4792925 (1988-12-01), Corda et al.
patent: 5110753 (1992-05-01), Gill et al.
patent: 5264384 (1993-11-01), Kaya et al.
patent: 5304829 (1994-04-01), Mori et al.

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