Transparent system interrupts with automated input/output trap r

Details Transparent system interrupts with automated input/output trap r Transparent system interrupts with automated input/output trap r

1993-04-26

1993-12-28

Eng, David Y.

395375, 395425, G06F 946, G06F 1214, G06F 1324

Patent

active

052748260

ABSTRACT:
A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by the bus unit. A dedicated memory area is provided for storing a customizable system interrupt service routine, program state data at the time of interruption and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted and continued execution including automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.

REFERENCES:
patent: 3639911 (1972-02-01), Frieband
patent: 3805245 (1974-04-01), Brooks
patent: 4404628 (1983-09-01), Angelo
patent: 4455622 (1984-06-01), Loskorn
patent: 4644494 (1987-02-01), Muller
patent: 5136714 (1992-08-01), Brandaway
patent: 5175853 (1992-12-01), Kardach et al.

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