High-gain semiconductor device with capacitive coupling

Details High-gain semiconductor device with capacitive coupling High-gain semiconductor device with capacitive coupling

1984-02-28

1986-12-30

Carroll, J.

357 20, 357 34, 357 35, H01L 2972, H01L 2702, H01L 2906

Patent

active

046332910

ABSTRACT:
An n-type region isolated by a p-type region is formed on a p-type substrate. Within the n-type region, in order to constitute an npn-transistor, an n.sup.+ region, a p-type region and an n.sup.+ region are formed. Within the n-type region, a p-type region is formed, and an insulating film and a metal layer are successively stacked on the p-type region to form an oxide film capacitor. The p-type region of the oxide film capacitor is in contact with the n.sup.+ region of the npn-transistor by means of a metal wiring. Within a p-type region of the oxide film capacitor, an n.sup.+ region is further formed. An additional npn-transistor may be formed by the n.sup.+ region, the p-type region and n-type region.

REFERENCES:
patent: 4211941 (1980-07-01), Schade, Jr.
patent: 4245231 (1981-01-01), Davies
patent: 4377029 (1983-03-01), Ozawa
C. Benichou et al., "Additional Capacitor to Reduce the Rate Effect Sensitive in a Thyristor", IBM Technical Disclosure Bulletin, vol. 24, (1981), pp. 107-108.
IBM Technical Disclosure Bulletin, vol. 20, No. 12, May 1978, p. 5137, "Enhanced Storage Medium for a Memory Cell", by A. Bhattacharyya et al.

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