Latch-up immune, multiple retrograde well high density CMOS FET

Details Latch-up immune, multiple retrograde well high density CMOS FET Latch-up immune, multiple retrograde well high density CMOS FET

1983-09-12

1986-12-30

Edlow, Martin H.

357 90, H01L 2702

Patent

active

046332898

ABSTRACT:
A high density CMOS device structure that is essentially immune to latch-up, and a method of fabricating the structure, is described. This is obtained by providing a well region within and adjacent a surface of a substrate, the well region having a multiple retrograde doping density profile, and by providing source and drain regions within the well and adjacent the surface of the substrate, the source and drain regions having associated therewith a greater than average density of residual defects within said well region, the greater density of residual defects being generally associated with the deepest portions of the source and drain regions and the immediately underlying portions of said well region, respectively.

REFERENCES:
patent: 4053925 (1977-10-01), Burr et al.
patent: 4167425 (1979-09-01), Herbst
patent: 4203126 (1980-05-01), Yim et al.
patent: 4216030 (1980-08-01), Graul et al.
patent: 4298401 (1981-11-01), Nuez et al.
Estreich, D. B., Ochoa, Jr. A., and Dutton, R. W., "An Analysis of Latch-Up Prevention . . . " IEDM Technical Digest, Dec. 1978, pp. 230-234.
Rung et al., "A Retrograde P-Well for Higher Density CMOS", IEEE Transactions on Elec. Dev., vol. ED-28, No. 10, Oct. 1981, pp. 1115-1119.
Electronics International, vol. 56, No. 15, Jul. 28, 1983 (New York, US) M. A. Harris: "Scaled-Down CMOS may Catapult GE to Chip Forefront", pp. 47-48, see page 47: FIG. 1.
IEEE Transactions on Nuclear Science, vol. NS-26, No. 6, Dec. 1979 (New York, US) A. Ochoa et al.: Ltch-Up Control in CMOS Integrated Circuits", pp. 5065-5068, see p. 5068, lines 1-14.
"Modeling Latch-Up in CMOS Integrated Circuits", by Donald B. Estreich, IEEE Transactions; vol. CAD-1, No. 4, Oct. 1982.

Affiliated with

Also associated with

Rating

Latch-up immune, multiple retrograde well high density CMOS FET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latch-up immune, multiple retrograde well high density CMOS FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latch-up immune, multiple retrograde well high density CMOS FET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1551105