Method of copy-back cache coherence control and tightly coupled

Details Method of copy-back cache coherence control and tightly coupled Method of copy-back cache coherence control and tightly coupled

1991-01-17

1993-12-28

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, G06F 1208

Patent

active

052747875

ABSTRACT:
A method of achieving consistent cache coherence control in a tightly coupled multi-processor system with a plurality of processors having copy-back cache memories and a shared memory connected by a split transfer system bus. In this method, the cache memory data management is accomplished by using cache memory states for labelling each data entry in the cache memories, the cache memory states including at least one transient state for awaiting data transfer after a corresponding address transfer, and access is prohibited to data which is in the transient state in one cache memory by a processor other that the processor associated with this one cache memory.

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Cache Coherency Protocol for Tightly Coupled Multiprocessor with Split Bus; Spring National Meeting of Electronic Information Communication Society (Mar. 1990); NTT Communications and Information Processing Laboratories. A translation is provided.
Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model; Association for Computing Machinery; ACM Transactions on Computer Systems, vol. 4, No. 4, Nov. 1986, pp. 273-298.
TRON Project 1990; Open-Architecture Computer Systems; Proceedings of the Seventh TRON Project Symposium; Ken Sakamura (ED.). Springer-Verlag, 1990.

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