Clock recovery circuit without jitter peaking

Details Clock recovery circuit without jitter peaking Clock recovery circuit without jitter peaking

1990-04-26

1991-07-30

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 25, 329325, H03L 700

Patent

active

050362984

ABSTRACT:
A voltage-controlled delay is connected in series with a phase-locked loop. The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter. With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.

REFERENCES:
patent: 4744096 (1988-05-01), Roux
patent: 4890071 (1989-12-01), Curtis
Trischitta, P. R. and Varma, E. L. Jitter in Digital Transmission Systems (Artech House, Norwood, MA 1989) Chapter 3, pp. 49-82.

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