High speed mask generation using selection logic

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3649292, 364947, 3649471, 3649474, 364950, 3649504, G06F 700

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057457441

ABSTRACT:
In a mask generator, decoders are provided for decoding respective portions of an input bit string into an intermediate string, and first and second selection signals. The intermediate string is placed into a first mask by a primary selection stage according to the first selection signals. The first mask is placed into a second mask by a secondary selection stage according to the second selection signals. The decoders are implemented using combinational logic, and the primary selectors are implemented using multiplexer and phase inverter circuits. Sixteen bit mask generation is realized from a 4-bit input string using only two decoders and a primary selector. Sixty-four bit mask generation is realized using a 6-bit input bit string and a secondary selector. The first and second masks contain two contiguous series of 1s and 0s. Parallel arrangements of mask generators are disclosed so that alternating series of 1s and 0s can be placed in output masks. Masks of arbitrary lengths can be produced using additional decoding and selectors.

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