Computer system including system controller with a write buffer

Details Computer system including system controller with a write buffer Computer system including system controller with a write buffer

1994-11-15

1998-04-28

Swann, Tod R.

395308, 395458, 395476, 395477, 395840, 395872, G06F 1300

Patent

active

057457328

ABSTRACT:
A computer system includes a processor having a cache memory and coupled to a system controller through a processor bus, a main memory coupled to the system controller through a dedicated memory bus, and a local bus master coupled to the system controller through a local bus. The system controller includes a write register and a read register that form a first path for coupling bus signals between the processor bus and main memory, and the system controller also includes a second read register that with the write buffer forms a second path to the main memory for coupling bus signals between the local bus and main memory. The first and second paths of the system controller decouple the processor and local buses, allowing processor-cache operations to proceed concurrently with operations between the local bus master and main memory. The first and second read buffers are fully snooped and implement replacement schemes that allow them to function as caches for the the processor and the local bus master, respectively, and a snoop tag register in the system controller stores recently snooped main memory addresses to eliminate redundant snoop cycles to the processor.

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