Method of manufacturing CMOS EPROM memory cells

Details Method of manufacturing CMOS EPROM memory cells Method of manufacturing CMOS EPROM memory cells

1988-07-25

1991-07-30

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, H01L 21265

Patent

active

050360183

ABSTRACT:
A method of manufacturing memory cells is described, wherein the great selectivity of polysilicon etching with respect to oxide is employed for the elimination of the self-aligned polysilicon mask for the definition of the floating gate of the EPROM cell. In fact, according to the invention, the mask for the formation of the source and drain regions of one of the CMOS transistors is used for the removal of the oxide separating the two layers of polysilicon on the active region defining a memory cell, and the mask for the formation of the source and drain regions of the other CMOS transistor is employed for the removal of the lower layer of polysilicon around the floating gate of the memory cell, wherein the silicon portions which are not to be removed are covered by oxide.

REFERENCES:
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4517732 (1985-05-01), Oshikawa
patent: 4598460 (1986-07-01), Owens et al.
patent: 4646425 (1987-03-01), Owens et al.
patent: 4696092 (1987-09-01), Doering et al.
patent: 4775642 (1988-10-01), Chang et al.

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