Fishing – trapping – and vermin destroying
Patent
1992-05-27
1993-12-28
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437919, 437978, 148DIG13, H01L 2176
Patent
active
052739279
ABSTRACT:
Problems arise when connecting the bottom plate of a ferroelectric capacitor to the source of its associated access transistor during the fabrication of an ultra large scale integrated memory circuit. The temperature and ambient of certain steps of the fabrication process adversely affects ohmic properties of the connection. To overcome these problems, an insulative layer is formed between the bottom plate of a ferroelectric capacitor and its associated transistor. The insulative layer separates the source from the bottom electrode, and subsequent high temperature swings during the remainder of the fabrication process do not produce any direct connection between the source and the bottom plate. After the memory circuits have been fabricated on the semiconductor wafer, a voltage is applied across the ferroelectric capacitor and the insulative layer, preferably during a wafer probe. The magnitude of the applied voltage is selected to breakdown the insulative layer, but does not damage the ferroelectric layer. As a result, a good ohmic contact is produced between the bottom plate and the source of its associated transistor.
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Chaudhari C.
Hearn Brian E.
Micro)n Technology, Inc.
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