Phase-locked loop and clock circuit for a line switch

Multiplex communications – Wide area network – Packet switching

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Details

370 84, H04J 306

Patent

active

045190712

ABSTRACT:
A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. First one processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit.
The second processor is used to select which of a plurality of sources may be used to provide clock signals within the line switch module.
A phase-locked loop permits clock signals which are generated in a line switch module to be in phase synchronism with any one of the PCM lines. When two or more lines switch modules are connected together to form a line switch, the phase-locked loop circuits of each module will utilize the same PCM line for phase-locking.

REFERENCES:
patent: 3825683 (1974-07-01), Pitroda et al.
patent: 3936603 (1976-02-01), Guppy et al.
patent: 3980820 (1976-09-01), Niemi et al.
patent: 4059805 (1977-11-01), de Laage de Meux et al.
patent: 4129748 (1978-12-01), Saylor
patent: 4321483 (1982-03-01), Dugan
W. Waggener, "Designer's Guide To: Digital Synchronization Circuits, Part III", EDN Magazine, vol. 21, No. 16, Sep. 1976, pp. 99-105.
J. Snyder, "Digital Phase-Locked Loop Finds Clock Signal in Bit Stream", Electronics, Aug. 30, 1979, vol. 52, No. 18, pp. 126-130.

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