Method for fabricating bipolar junction and MOS transistors on S

Details Method for fabricating bipolar junction and MOS transistors on S Method for fabricating bipolar junction and MOS transistors on S

1992-10-05

1993-12-28

Thomas, Tom

Fishing, trapping, and vermin destroying

437 31, 437 59, 437 60, 148DIG9, 148DIG150, H01L 21265

Patent

active

052739155

ABSTRACT:
An SOI wafer (10) is separated into a bipolar junction transistor area (18) and an MOS transistor area (19). A bipolar junction transistor having a collector region (25), and emitter region (44), an inactive base region (33), and an active base region (43) is formed on a thin film of semiconductor material (13) in the bipolar junction transistor area (18). A link between the inactive base region (33) and the active base region (43) is formed from a polysilicon spacer (42) along an edge or sidewall of emitter openings (39 or 40). Simultaneously with the formation of the bipolar junction transistor, MOS transistors are formed in the MOS transistor area (19). Electrically conductive contacts (56) in the bipolar junction transistor area (18) and the MOS transistor area (19) are formed from a silicide. Both complementary bipolar junction transistors and MOS transistors may be formed.

REFERENCES:
patent: 5049513 (1991-09-01), Eklund
patent: 5100810 (1992-03-01), Yoshimi et al.
patent: 5145796 (1992-09-01), Adan et al.
patent: 5164326 (1992-11-01), Foerstner et al.

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