Protection device for an intergrated circuit and method of forma

Active solid-state devices (e.g. – transistors – solid-state diode – Punchthrough structure device

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257498, 437 20, 437 28, 437 67, 437228, H01L 2990, H01L 21265

Patent

active

054061113

ABSTRACT:
An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.

REFERENCES:
patent: 4466180 (1984-08-01), Soclof
Krakauer et al., "ESD Protection in a 3.3V Sub-Micron Silicided CMOS Technology," Electrical Overstress/Electrostatic Discharge Symposium Proceedings, Sep. 16, 1992, pp. 250-257.
Charvaka Duvvury, "ESD Reliability for Advanced CMOS Technologies," 1990 International Electron Devices and Materials Symposium, Nov. 14, 1990, pp. 265-272.

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