Systematic symbol level ECC for use in digital memory systems

Details Systematic symbol level ECC for use in digital memory systems Systematic symbol level ECC for use in digital memory systems

1995-03-31

1998-04-28

Baker, Stephen M.

Excavating

G06F 1110

Patent

active

057455074

ABSTRACT:
A method is provided for the construction of systematic error correction codes having double symbol error detection and single symbol correction capabilities. These systematic codes are employed in conjunction with digital memory systems in which the same electrical circuit mechanism is employed for check bit generation and syndrome generation. As a result, the number of circuit levels is reduced, the circuit operates faster, and yet at the same time efficiencies of space or chip "real estate" utilization are achieved since fewer circuits are required to achieve the same objectives, especially with respect to encoding and syndrome generation.

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