Means and method of reducing the number of masks utilized in fab

Details Means and method of reducing the number of masks utilized in fab Means and method of reducing the number of masks utilized in fab

1973-07-26

1982-01-12

Smith, Jr., David

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, H01L 2116, H01L 21283

Patent

active

043098118

ABSTRACT:
A plurality of integrated circuit wafers each having a plurality of cells disposed in a rectilinear array with the yield distribution of usable cells varying from wafer to wafer but in which there is a common yield distribution of at least Y usable cells or portions thereof in corresponding locations on N wafers (where Y and N are integers); a layer of electrical insulation that exposes the pads of the Y common yield distribution usuable circuits to a second level of metalization which is formed into conductors by a first pad relocation mask which is common to the N wafers for effectively routing the exposed pads of the Y usable cells to master pattern circuit locations; and a layer of electrical insulation formed over the second level of metalization having master pattern vias formed therethrough which expose the pads at master pattern cell locations to a top layer of metalization formed into a common or master pattern of interconnects which interconnect the cells into the specific circuit type by a master pattern mask common to the Y wafers and a plurality of other wafers to be connected into the specific circuit type.

REFERENCES:
patent: 3423822 (1969-01-01), Davidson et al.
patent: 3434020 (1969-03-01), Ruggiero
patent: 3498833 (1970-03-01), Lehrer
patent: 3518751 (1970-07-01), Waters et al.
patent: 3615466 (1971-10-01), Sahni
patent: 3618201 (1971-11-01), Makimoto et al.
patent: 3627598 (1971-12-01), McDonald

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