Method of forming a vertical transistor

Details Method of forming a vertical transistor Method of forming a vertical transistor

1990-07-30

1994-03-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 62, 437 67, 437974, 148DIG85, 148DIG135, H01L 21265

Patent

active

052945596

ABSTRACT:
A vertical transistor comprises a semiconductor layer of a first conductivity type having a first doped region (48) formed therein. A second doped region (50) is formed within the first doped region (48). A gate overlies the first doped region such that a low impedance path between the second doped region and the semiconductor layer may be created responsive to a voltage applied to the gate. Isolation regions (38 and 58) are formed through the semiconductor layer to isolate the transistor from other devices.

REFERENCES:
patent: 4837186 (1989-06-01), Ohata et al.

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