Boots – shoes – and leggings
Patent
1979-12-06
1982-08-10
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 300
Patent
active
043441319
ABSTRACT:
A circuit arrangement for reducing access time to information contained in a memory system that includes a register for collecting the information contained in the memory system. The register operates as a flip-flop and is composed of a first inverter, an AND gate and a second inverter. The input of the first inverter is connected to receive the information bits read in a memory block. The AND gate includes two inputs, one of which is connected to the output of the first inverter. The other input receives, at the beginning of the memory reading cycle, an initialization signal for positioning the flip-flop in a given state. The output of the AND gate is connected to the second inverter which has its output connected, in turn, to the input receiving information read from the memory system.
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patent: 3492658 (1970-01-01), Klett
patent: 3571808 (1971-02-01), Washizuka et al.
patent: 3801965 (1974-04-01), Berger et al.
patent: 3848232 (1974-11-01), Leibler et al.
patent: 4012721 (1977-03-01), Lindsay
Compagnie Internationale pour l' Informatique CII-Honeywell Bull
Heckler Thomas M.
Kondracki Edward J.
Shaw Gareth D.
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