Static information storage and retrieval – Floating gate – Particular biasing
Patent
1996-02-02
1997-06-24
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
36518909, 36518527, G11C 700
Patent
active
056423101
ABSTRACT:
A double erase control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. A host selectively erases flash memory cells by placing 0 VDC on the word lines and a large positive voltage (10.4 VDC to 10.8 VDC) on an array virtual ground supply (VVSS) line while the drains of the memory cells float. The voltage and current on the VVSS line are simultaneously controlled using voltage and current control circuitry that are responsive to a high erase signal that is asserted by the host during an erase operation. When the erase signal is high, the voltage control circuitry uses a comparator, a stable reference voltage (1.28 VDC) derived from a band-gap reference and a feedback loop to maintain VVSS at the target source erase voltage (i.e., 10.4 VDC to 10.8 VDC). Simultaneously, the current control circuitry limits current on the VVSS line to approximately 10 mA through the use of a transistor that draws a known bias current and a current mirror that amplifies and mirrors the amplified bias current onto the VVSS line. When the host deasserts the erase signal, the double erase circuitry is disabled and VVSS is coupled to the circuit ground node.
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Integrated Silicon Solution Inc.
Le Vu A.
Nelms David C.
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