Forming a bit line configuration for semiconductor memory

Details Forming a bit line configuration for semiconductor memory Forming a bit line configuration for semiconductor memory

1992-05-14

1994-03-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437195, 437 49, H01L 21265

Patent

active

052926788

ABSTRACT:
A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts and with two different interconnecting layers and in an alternating row order, the true and complement bit lines and will run parallel to both sides of the memory array. In another embodiment, referred to as the side wall bit line structure, the bit lines are constructed by using the conductive side wall spacer rails to connect the interdigitated cells associated to it. By connecting the side wall bit line contacts with two sided-side wall spacer rails in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array.

REFERENCES:
patent: 4576900 (1986-03-01), Chiang
patent: 4833518 (1989-05-01), Matsuda et al.
patent: 4937649 (1990-06-01), Shiba et al.
patent: 5084414 (1992-01-01), Manley et al.
patent: 5172202 (1992-12-01), Kazuo
Patent Abstracts of Japan, vol. 12, No. 351 (E-660) (3198) Sep. 20, 1988 and JP 63-108764 (NEC Corp).
IBM Technical Disclosure Bulletin, "Folded Bitline Configuration", vol. 30, No. 3, Aug. 1987, pp. 1314-1315.

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