Memory input buffer with hysteresis and dc margin

Details Memory input buffer with hysteresis and dc margin Memory input buffer with hysteresis and dc margin

1987-12-28

1989-02-21

Fears, Terrell W.

Static information storage and retrieval

Addressing

365189, 365190, G11C 1140, G11C 1300

Patent

active

048071986

ABSTRACT:
A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.

REFERENCES:
patent: 4769789 (1988-09-01), Noguchi et al.

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