Reduced mask CMOS process for fabricating stacked capacitor mult

Details Reduced mask CMOS process for fabricating stacked capacitor mult Reduced mask CMOS process for fabricating stacked capacitor mult

1992-09-18

1994-03-08

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

052926770

ABSTRACT:
An etch stop layer is deposited on a DRAM wafer after formation of the PMOS and NMOS transistors and A.A's. After deposition of oxide 1, a first mask and etch process is used to form the capacitor container and remove the oxide 1 and etch stop at the future poly 1 and cell poly contacts. After deposition of the capacitor, a second mask and etch removes the capacitor layers at the future poly 1 contact. After deposition of oxide 2 and a poly etch stop layer, a third mask and etch process forms the bit line contact region through the cell poly, and the poly 1 and cell poly contact region. The etch is made through the cell poly at the bit line contact and a thin oxide is deposited and etched to form cell poly spacers that don't close off the active area. An oxide etch goes to the etch stop layer at the bit contact region, to the poly 1 at the future poly 1 contact, and to the cell poly at the future cell poly contact. After etch of the etch stop at the future bit line contact, the contacts are formed.

REFERENCES:
patent: 5087591 (1992-02-01), Teng
patent: 5118382 (1992-06-01), Cronin et al.
Kawamoto et al., "A 1.28.mu.m.sup.2 Bit-Line Shielded Memory Cell Technology for 64Mb DRAMS", Symposium on VLSI Technology, 1990, pp. 13-14.
Itoh et al., "Two Step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact Penetrating Cellplate (SABPEC) for 64 MbDRAM STC Cell" IEEE Symposium on VLSI Technology, 1991, pp. 9-10.
Shibata et al., "A Novel Zero-Overlap/Enclosure Metal Interconnection Technology for High Density Logic VLSI's", IEEE VMIC Conference, 1990, pp. 15-21.

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