Turn off delay reduction circuit and method

Details Turn off delay reduction circuit and method Turn off delay reduction circuit and method

1991-11-29

1993-04-20

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307300, 3072471, 307270, 307279, H03K 17687, H03K 333

Patent

active

052045625

ABSTRACT:
A gate driver circuit for switching a MOSFET on and off while reducing the turn off delay of the MOSFET without effecting the turn off slew rate thereof includes a low impedance circuit path between the gate and drain of the MOSFET which is responsive to a control signal for providing discharge of the gate capacitance and a controlled current discharge path for controlling the slew rate of the drain voltage. The low impedance circuit path is automatically disabled once the threshold voltage of the MOSFET is reached and the MOSFET begins to turn off as the drain voltage reaches a predetermined level. As the low impedance circuit path is disabled the controlled current discharge path fixes the slew rate or dv/dt of the drain to source voltage during turn off of the MOSFET.

REFERENCES:
patent: 4051588 (1977-09-01), Inukai
patent: 4531068 (1985-07-01), Kraft et al.
patent: 4891532 (1990-01-01), Shekhawat et al.
patent: 4906867 (1990-03-01), Petty

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