Digital signal level translator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307443, 307451, 307497, H03K 19094

Patent

active

052045579

ABSTRACT:
A low static power, digital signal level translator for translating an unbalanced digital signal to a balanced digital signal with a greater dynamic signal range includes two complementary MOSFET latches and a complementary MOSFET output buffer amplifier. The two latches each receive an unbalanced digital input signal (e.g. with TTL voltage levels) and translate it to a second unbalanced digital signal and an asymmetrically balanced digital signal. The symmetrically biased, output buffer amplifier receives these signals and produces therefrom a symmetrically balanced digital output signal with a greater dynamic signal range (e.g. with .+-.10 volt levels). Various embodiments include two gate-driven complementary MOSFET latches, two source-driven complementary MOSFET latches or a combination of gate-driven and source-driven complementary MOSFET latches, each of which includes a pair of cross-coupled complementary MOSFET totem-pole amplifiers, for providing the second unbalanced digital signal and the asymmetrically balanced digital signal. Each embodiment further includes a complementary MOSFET totem-pole output buffer amplifier as the symmetrically biased, output buffer amplifier for providing the symmetrically balanced digital output signal.

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