1987-04-08
1989-02-21
Carroll, J.
357 231, 357 65, 357 68, 357 71, H01L 2978, H01L 2904, H01L 2348
Patent
active
048070130
ABSTRACT:
Disclosed is an integrated circuit manufacturing technique that relies on the use of polysilicon fillets for overcoming the well known adverse effects of steep sidewalls produced by anisotropic etching processes and undercuts produced by anisotropic etching of multilayers.
REFERENCES:
patent: 4234362 (1980-11-01), Riseman
patent: 4312680 (1982-01-01), Hsu
patent: 4319261 (1982-03-01), Kub
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4374700 (1983-02-01), Scott et al.
patent: 4406051 (1983-09-01), izuka
patent: 4419809 (1983-12-01), Riseman
patent: 4478679 (1984-10-01), Chang et al.
patent: 4507171 (1985-03-01), Bhatia et al.
patent: 4507853 (1985-04-01), McDavid
patent: 4691435 (1987-09-01), Anantha et al.
F. Barson, "Modified Polysilicon Emitter Process", IBM Technical Disclosure Bulletin, vol. 22 (1980) pp. 4052-4053.
P. J. Tsang, "Method of Forming Poly-si Pattern with Tapered Edge", IBM Technical Disclosure Bulletin, vol. 19 (1976) pp. 2047-2048.
W. R. Hunter et al, "A New Edge-Defined Approach For Submicrometer MOSFET Fabrication", IEEE Electron Device Letters, vol. EDL-2, No. 1 (Jan., 1981) pp. 4-6.
American Telephone and Telegraph Company AT&T Bell Laboratories
Carroll J.
Rehberg John T.
LandOfFree
Polysilicon fillet does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Polysilicon fillet, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Polysilicon fillet will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1526466