Fishing – trapping – and vermin destroying
Patent
1990-09-04
1993-04-20
Thomas, Tom
Fishing, trapping, and vermin destroying
437 47, 437 48, 437 60, 437203, 437233, 437919, 257296, H01L 2170
Patent
active
052042812
ABSTRACT:
A trench is formed in a substrate and lined with a dielectric. A first silicon layer of a first conductivity is deposited in the trench. A second silicon layer of a second conductivity type is deposited over the first layer and a third silicon layer of the first conductivity type is deposited on the second layer, all are disposed within the trench area. A second trench is then formed through the third and second layers and into the first layer. The second trench is then lined with a dielectric and filled with a gate polysilicon. The appropriate connections are then made to the gate, the third layer, and the substrate.
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IBM TDB, vol. 22, No. 813, Jan. 1980, Vertical FET Random-Access Memories with Deep Trench Isolation.
Dockrey Jasper W.
Motorola Inc.
Thomas Tom
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