Communications: electrical – Digital comparator systems
Patent
1976-12-15
1979-01-02
Yusko, Donald J.
Communications: electrical
Digital comparator systems
178 4, 178 30, 364900, H04L 1534, H04Q 347, G06F 504, G05B 1502
Patent
active
041329791
ABSTRACT:
A circuit is described for controlling a programmable logic array adapted for use with a communications terminal. The logic array includes an input AND-section defined by a plurality of addressable fields and an output OR-section. One field of the input section is addressed by an incoming address register selectively loaded with incoming data. A second field is addressed by a branch address register loaded with selective outputs of the output section thus providing program branching capabilities. Also, a loop counter and a clocked program counter address two additional fields of the input section. The loop counter facilitates program looping in the logic array while the program counter affords real time operational characteristics for the control circuit.
REFERENCES:
patent: 3823397 (1974-07-01), Howard et al.
patent: 3924225 (1975-12-01), Langnickel
patent: 3987286 (1976-10-01), Muehldorf
patent: 4020465 (1977-04-01), Cochran et al.
patent: 4031519 (1977-06-01), Findley et al.
patent: 4037089 (1977-07-01), Horninger
GP Check et al., "Programmable Stepper Motor Control" IBM Technical Disclosure Bulletin, vol. 17, No. 11, pp. 3390-3391, Apr. 1975.
Albrecht J. C.
Serp W. K.
Teletype Corporation
Yusko Donald J.
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