Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-12-24
1999-09-14
Nguyen, Viet Q.
Static information storage and retrieval
Floating gate
Particular biasing
3651853, 36518533, 36518528, G11C 1140
Patent
active
059532556
ABSTRACT:
An array of MOS memory cells having functionally symmetrical drain and source regions may be programmed and/or erased using low voltage, e.g., less than about 7V. In a NAND-type array, UV-erasure increases threshold voltage Vt to erase memory cell contents, and low voltage-low current hot-hole injection ("HHI") decreases Vt to program the memory cells. For NOR-type arrays, HHI decreases Vt to erase memory cell contents and channel-hot-electron ("CHE") injection increases Vt to program cell contents. Erase and program potentials are low (<7V), enabling arrays to be readily fabricated on a common IC with low voltage circuits. Because HHI strongly converges Vt, the memory cells may store more than two data values, which increases cell storage density. Cell symmetry permits swapping drain for source before cell endurance becomes too troublesome, which swapping can substantially increase the endurance lifetime for an array. Arrays may be used as flash memory, as EPROM replacement, or as one-time-programmable memory.
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Aplus Flash Technology Inc.
Nguyen Viet Q.
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