Boots – shoes – and leggings
Patent
1997-06-23
1999-09-14
Ngo, Chuong Dinh
Boots, shoes, and leggings
364788, 371 53, G06F 1100, G06F 1110, G06F 750
Patent
active
059532408
ABSTRACT:
A CPU adapted to calculate a checksum simultaneously on multiple values packed into a single register. An adder is provided which adds a number of values packed into a first register to a number of packed values from a second register. The adder is constructed, or partitioned, so that the values do not propagate their carry bit to the next value. A special carry bit adder is provided which will add a carry bit out of each partitioned portion back into the sum value to generate the sum required by the checksum protocol.
REFERENCES:
patent: 5327369 (1994-07-01), Ashkenazi
Shipnes, "Graphic Processing with the 88110 RISC Microprocessor" IEEE, 1992, pp. 169-174.
Gentry Denton E.
Prabhu J. Arjun
Ngo Chuong Dinh
Sun Microsystems Inc.
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