Semiconductor integrated circuit achieving reliable data latchin

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327158, 375376, H03K 500, H03K 513

Patent

active

059528575

ABSTRACT:
A semiconductor integrated circuit receiving a plurality of input signals each exhibiting a signal-level change during a predetermined time span includes a timing-detection circuit which detects timing of said signal-level change of said input signals, and detects which input signal is furthest behind in terms of a signal-level-change timing among said plurality of input signals within said predetermined time span. The semiconductor integrated circuit further includes first delay-adjustment circuits which delay said plurality of input signals, respectively, in response to an output signal from the timing-detection circuit to generate delayed input signals such that signal-level-change timings of said delayed input signals are aligned to said signal-level-change timing of said furthest behind input signal, and latch circuits each latching a respective one of said delayed input signals at the same timing.

REFERENCES:
patent: 5150068 (1992-09-01), Kawashima et al.
patent: 5486783 (1996-01-01), Baumert et al.
patent: 5663668 (1997-09-01), Hayashi et al.

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