Numerical arithmetic processing unit

Details Numerical arithmetic processing unit Numerical arithmetic processing unit

1994-09-15

1996-07-02

Envall, Jr., Roy N.

Boots, shoes, and leggings

3647365, G06F 738, G06F 700

Patent

active

055329381

ABSTRACT:
Arithmetic units are supplied with instructions from a control unit in common through an instruction broadcast bus. Each of the arithmetic units includes a process data input port, an address data input port, a process data output port and an address data output port. Address data appearing on the address ports specify addresses of a local memory. Each of the arithmetic units reads corresponding numeric data from the local memory and executes arithmetic processing in accordance with the instruction supplied from the control unit through a computing element group and a register group. In each arithmetic unit, it is possible to specify addresses of the local memory independently of each other. Each unit include circuitry for omitting an arithmetic operation on data read from the local memory when the read out data is negligible.

REFERENCES:
patent: 5175858 (1992-12-01), Hammerstrom
patent: 5260897 (1993-11-01), Toriumi et al.
patent: 5307300 (1994-04-01), Komoto et al.
"Parallel Architectures for Artificial Neural Nets", IEEE International Conference on Neural Networks, San Diego, vol. II, pp. 165-172, Jul. 1988, by S. Y. Kung and J. N. Hwang.
"Snap Technical Description", HNC Inc. Apr. 1993.

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