System for performing I/O access and memory access by driving ad

Details System for performing I/O access and memory access by driving ad System for performing I/O access and memory access by driving ad

1993-10-29

1996-10-01

Lee, Thomas C.

Boots, shoes, and leggings

395842, 395846, 3642423, 36424234, 3649481, G06F 1328

Patent

active

055618219

ABSTRACT:
A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer. Since the memory access cycle and the I/O access cycle of the DMA transfer are identical to those executed by the system microprocessor, subsystems are not required to respond to specialized DMA protocols. Finally, although the DMA controller implements two-cycle DMA transfers, the DMA controller is compatible with conventional peripheral devices which assume one-cycle DMA transfer protocols.

REFERENCES:
patent: 4815034 (1989-03-01), Mackey
patent: 5077664 (1991-12-01), Taniai et al.
patent: 5287457 (1994-02-01), Arimilli et al.
patent: 5297242 (1994-03-01), Miki
"I/O Address Decoding System," Patent Abstracts of Japan, vol. 12 No. 231, Jun. 30, 1988, p. 723.

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