Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Patent
1995-03-10
1996-07-02
Cunningham, Terry
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
327157, 327538, H03L 706
Patent
active
055326366
ABSTRACT:
A charge pump circuit suitable for use in a high frequency phase locked loop. The charge pump circuit comprises a biasing circuit, a charging transistor, a discharging transistor, and a pair of complementary switches. The charging transistor may be a p-channel field effect transistor (FET), and the discharging transistor may be a matched n-channel FET. The drains of the charging and discharging transistors are coupled together to form an output node for the charge pump circuit, and the biasing circuit provides a biasing voltage to the gates of the charging and discharging transistors. A first complementary switch is coupled in series between a supply voltage VCC and the source of the charging transistor. Similarly, a second complementary switch is coupled in series between system ground VSS and the source of the discharging transistor. A first pair of complementary control signals control the first complementary switch to switch on and off to provide positive current pulses at the output node, while a second pair of complementary control signals control the second complementary switch to switch on off to provide negative current pulses at the output node.
REFERENCES:
patent: 4633488 (1986-12-01), Shaw
patent: 5144156 (1992-09-01), Kawasaki
patent: 5182529 (1993-01-01), Chern
patent: 5264743 (1993-11-01), Nakagome et al.
patent: 5285114 (1994-02-01), Atriss et al.
patent: 5362990 (1994-11-01), Alvarex et al.
patent: 5376848 (1994-12-01), Hanke, III et al.
patent: 5399928 (1995-03-01), Lin et al.
D. K. Jeong, G. Boriello, D. A. Hodges, and R. H. Katz, "Design of PLL-Based Clock Generation Circuits", IEEE Journal of Solid State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261.
A. Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock", ISSCC Digest of Technical Papers, Fe. 1994, pp. 298-299.
M. G. Johnson and E. L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessory Synchronization", IEEE Journal of Solid State Circuits, vol. 23, No. 5, Oct. 1988 pp. 1218-1223.
L. A. Young, J. K. Greason, and K. L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", vol. 27, No. 11, Nov. 1992, pp. 1599-1606.
J. Alvarez, H. Sanchez, G. Gerosa, C. Hanke, R. Countryman and S. Thadasina, "A Wide-Bandwidth Low-Voltage PLL for PowerPC", Digest of Papers, Symposium on VLSI Circuits, Honolulu, Jun. 9-11, 1994.
Madland Paul D.
Mar Monte F.
Cunningham Terry
Intel Corporation
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