Parallel processing apparatus and method capable of processing p

Details Parallel processing apparatus and method capable of processing p Parallel processing apparatus and method capable of processing p

1994-12-20

1996-10-01

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 3642287, 364229, 364230, 3642303, 3642319, G06F 9445

Patent

active

055617751

ABSTRACT:
A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations. The branch arithmetic unit is controlled by the control unit to effect parallel or consecutive processing of instructions in conjunction with the integer-logic and floating-point arithmetic units.

REFERENCES:
patent: 4476525 (1984-10-01), Ishii
patent: 4594655 (1986-06-01), Hdo et al.
patent: 4626989 (1986-12-01), Torii
patent: 4644466 (1987-02-01), Saito
patent: 4794517 (1988-12-01), Jones et al.
patent: 4916606 (1990-04-01), Yamaoka et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 5101341 (1992-03-01), Circello et al.
David T. Hilja "Reducing the Branch Penalty in Pipe-line Processors" Computer (Jul. 1988) pp. 47-55.
Miller et al. "Floating-Duplex Decode and Execution of Instructions", IBM Technical Disclosure Bulletin (vol. 23, No. 1) (Jun. 1980) pp. 409 to 412.

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