Latching sense amplifier for a programmable logic device

Static information storage and retrieval – Floating gate – Particular biasing

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36518529, 36518905, 365207, 327 51, G11C 700

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active

055616291

ABSTRACT:
A sense amplifier is provided that automatically determines its enabled/disabled state. The sense amplifier includes a latch to store the enable/disable signals. A global power-on-reset signal during initialization sets the state of this latch to a default configuration which disables, i.e. powers down, the sense amplifier. During configuration, an active latch enable signal forces the sense amplifier into an enable ready state. Then, a high signal is provided to each wordline associated with the bitline of the sense amplifier. This causes any erased memory cell driven by the wordlines to pull the associated bitline into a bitline low state and causes the sense amplifier output signal to switch states. This switch causes the latch to be overwritten with the opposite state, thereby enabling the sense amplifier. When the latch enable signal goes inactive after configuration of the device, the latch is set such that the sense amplifier remains enabled, i.e. powered up. If there are no erased cells on the bitline, i.e. all of the cells are programmed, then the sense amplifier output signal remains the same, and the latch is not overwritten. Thus, when the latch enable signal returns to a high state, the sense amplifier remains disabled. Therefore, any sense amplifier that is not needed in the design, indicated by the lack of erased memory cells, remains disabled. In this manner, the present invention advantageously powers down all unused sense amplifiers automatically, thereby significantly reducing power consumption and minimizing overhead while maximizing the programmability of the device.

REFERENCES:
patent: 5023838 (1991-06-01), Herbert
patent: 5267203 (1993-11-01), Hwang et al.
patent: 5377150 (1994-12-01), McClure
patent: 5386389 (1995-01-01), Taoka

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