Structure and method for multiple-level read buffer supporting o

Details Structure and method for multiple-level read buffer supporting o Structure and method for multiple-level read buffer supporting o

1995-04-13

1997-07-15

Swann, Tod R.

Boots, shoes, and leggings

395849, 395878, 395494, 395450, 395250, 395821, 364DIG1, G06F 1314

Patent

active

056492324

ABSTRACT:
A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable RdCEn and acknowledge (Ack) signals. The RdCEn signal is provided as each memory word is available from the main memory. The Ack signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.

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patent: 5179709 (1993-01-01), Bailey et al.
A. J. Smith, "Sequential Program Prefetching in Memory Hierarchies", IEEE Computer, Dec. 1978, pp. 7-21.
Gindele, "Buffer Block Prefetching Method", IBM Technical Disclosure Bulletin, Jul. 1977, vol. 20, No. 2, pp. 696-697.
Pomerene et al., "Base/Displacement Lookahead Buffer", IBM Technical Disclosure Bulletin, Apr. 1980, vol. 22, No. 11, p. 5182.

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