Pipeline data processor with arithmetic/logic unit capable of pe

Details Pipeline data processor with arithmetic/logic unit capable of pe Pipeline data processor with arithmetic/logic unit capable of pe

1995-04-10

1997-07-15

Donaghue, Larry D.

Boots, shoes, and leggings

395376, 3642318, 364258, 3642633, 364DIG1, G06F 1300

Patent

active

056492294

ABSTRACT:
The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

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patent: 5091853 (1992-02-01), Watanabe et al.
patent: 5187795 (1993-02-01), Balmforth et al.
patent: 5197141 (1993-03-01), Ito
DeRosa et al., "An Evaluation of Branch Architectures", IEEE Computer Architecture, 1987, pp. 10-16.
McFarling et al., "Reducing the Cost of Branches", IEEE 13th International Symposium on Computer Architecture, 1986, pp. 396-403.

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