Apparatus and method for providing a cache indexing scheme less

Details Apparatus and method for providing a cache indexing scheme less Apparatus and method for providing a cache indexing scheme less

1995-06-02

1997-07-15

Asta, Frank J.

Boots, shoes, and leggings

395403, 395420, 39542102, 39542106, 395445, 395474, 364DIG1, G06F 1200

Patent

active

056491433

ABSTRACT:
Logic circuitry and a corresponding method for computing an indexed set address utilized by a cache to mitigate the probability of a conflict miss occurring for a given memory access. Implemented at component or system level, the logic circuitry performs pseudo-random indexing of a set address obtained from a memory address during a memory access by a processor unit. This is accomplished by performing operations consistent with modulo operations on the memory address.

REFERENCES:
patent: 5379393 (1995-01-01), Yang
patent: 5509135 (1996-04-01), Steely, Jr.
"Introducing a New Cache Design Into Vector Computers", Qing Yang, IEEE Transactions on Computers, vol. 42, No. 12, Dec. 1, 1993, pp. 1411-1424.
"A Case for Two-Way Skewed-Associative Caches", Andre Seznec, Proceedings of the Annual International Symposium on Computer Architecture, San Diego, May 16-19, 1993, No. Symp. 20 May 16, 1993, Institute of Electrical and Electronics Engineers, pp. 169-178.

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