Parallel signal bus with reduced miller effect capacitance

Details Parallel signal bus with reduced miller effect capacitance Parallel signal bus with reduced miller effect capacitance

1995-12-04

1997-07-15

Ray, Gopal C.

G06F 1340

Patent

active

056491263

ABSTRACT:
A parallel signal bus for conveying a plurality of logic signals with reduced Miller effect capacitance includes adjacent, parallel signal lines with inverting buffer amplifiers whose respective positions are staggered both longitudinally along the signal lines and latitudinally with respect to their adjacent signal lines. With such a staggered configuration, the resulting Miller effect capacitance which would otherwise result from adjacent signal lines being driven at opposing polarities is reduced, on average, by approximately half.

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Tsutomu Yoshihara, Hideto Hidaka, Yoshio Matsuda and Kazuyasu Fujishima, "A Twisted Bit Line Technique for Multi-Mb DRAMs", IEEE International Solid-State Circuits Conference, Feb. 19, 1988, pp. 238 and 239.

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