Processor for executing highly efficient VLIW

Details Processor for executing highly efficient VLIW Processor for executing highly efficient VLIW

1998-06-12

2000-07-04

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Long instruction word

712 23, 712208, 712210, 712212, G06F 928

Patent

active

060853069

ABSTRACT:
A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code "cc" that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant "const". The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.

REFERENCES:
patent: 5530817 (1996-06-01), Masubuchi
patent: 5535410 (1996-07-01), Watanabe et al.
patent: 5734913 (1998-03-01), Iwamura et al.
patent: 5748936 (1998-05-01), Karp et al.
patent: 5761470 (1998-06-01), Yoshida
patent: 5881307 (1999-03-01), Park et al.

Affiliated with

Also associated with

Rating

Processor for executing highly efficient VLIW does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor for executing highly efficient VLIW, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor for executing highly efficient VLIW will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1496351