Fast and normal rate instruction fetching

Details Fast and normal rate instruction fetching Fast and normal rate instruction fetching

1976-06-15

1978-06-06

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 906

Patent

active

040939839

ABSTRACT:
Instruction processing rate in a computer system is increased by providing a high speed data path to central processing unit (CPU) registers and including an auxiliary arithmetic and logic unit to enable updating the instruction address register (IAR) in one operation concurrently with a storage fetch whereby two storage fetches can be made within a single machine cycle. Normal instruction rate processing is retained by generating idle or dummy half cycles to enable a single storage fetch per machine cycle and thereby maintain flexibility for I/O instruction processing, for diagnostic purposes and for fetching the last byte or segment of an instruction having an odd number of bytes or segments.

REFERENCES:
patent: 3408630 (1968-10-01), Packard et al.
patent: 3657705 (1972-04-01), Mekota, Jr. et al.
patent: 3990052 (1976-11-01), Gruner

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