Boots – shoes – and leggings
Patent
1978-07-03
1981-10-20
Shaw, Gareth D.
Boots, shoes, and leggings
365230, G11C 1300
Patent
active
042964679
ABSTRACT:
A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.
REFERENCES:
patent: 3736574 (1973-03-01), Gersbach
patent: 3872452 (1975-03-01), Stoops
patent: 3898631 (1975-08-01), Brown
patent: 3913072 (1975-10-01), Catt
patent: 3949378 (1976-04-01), Crabb
patent: 3972025 (1976-07-01), Taddei
patent: 4001786 (1977-01-01), Boehm
Design of Digital Computers, Hans Gischwind, 1975 by Springer-Verlag, New York, pp. 233-239.
Nibby, Jr. Chester M.
Panepinto, Jr. William
Driscoll Faith F.
Eng David Y.
Honeywell Information Systems Inc.
Prasinos Nicholas
Shaw Gareth D.
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