Method for producing semiconductor memory device having a capaci

Details Method for producing semiconductor memory device having a capaci Method for producing semiconductor memory device having a capaci

1998-08-18

2000-07-04

Tsai, Jey

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

438240, 438253, H01L 218242

Patent

active

060837659

ABSTRACT:
A semiconductor memory device includes a semiconductor substrate having a surface defining a plane extending substantially parallel thereto. A multiplicity of memory cells disposed on the substrate each have a selection transistor disposed in the plane. The transistor has a gate terminal and first and second electrode terminals. Each of the memory cells has a storage capacitor associated with and triggerable by the transistor. The capacitor has a ferroelectric dielectric and first and second capacitor electrodes. The capacitor has a configuration projecting upward from the plane and is disposed inside a trench extending as far as the second electrode terminal of the transistor. A word line is connected to the gate terminal of the transistor, a bit line is connect to the first electrode terminal of the transistor, and a common conductor layer of electrically conductive material is connected to the first capacitor electrode of the capacitor. A method for producing the device includes producing the capacitor after production of the transistor and metallizing layers associated with the transistor for connection of the word and bit lines, in a configuration projecting upward from the plane, and placing the capacitor inside a trench extending as far as the second electrode terminal of the transistor.

REFERENCES:
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patent: 5837591 (1999-11-01), Shimada et al.
patent: 5985713 (1999-11-01), Bailey
"Ferroelectrics and High Permittivity Dielectrics for Memory Applications" (Larsen et al.), dated Aug., 1993, Microelectronic Engineering Nos.1/4, pp. 53-60, Amsterdam.
"Integration of Ferroelectric Capacitor Technology with CMOS" (Moazzami et al.), 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 55-56.
"A 256kb Nonvolatile Ferroelectric Memory at 3V and 100ns" (Tatsumi et al.), 1994 ISSCC, Session 16, Technology Directions: Memory, Packaging, Paper FA 16.2, pp. 206-209 and 315-316.
"Recessed Memory Array Technology for a Double Cylindrical Stacked Capacitor Cell of 256M DRAM" (Sagara et al), dated Nov. 1992, IEICE Transactions on Electronics, vol. E75-C, No. 11.

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