Patent
1988-02-26
1991-06-18
Wojciechowicz, Edward J.
357 71, H01L 2348
Patent
active
050253034
ABSTRACT:
A process for the formation of pillars (28) in connection with the fabrication of a semiconductor device (10) is disclosed. The process first aligns a lead pattern (30) with an existing structure (24) in the semiconductor device (10). Next, the process aligns a pillar pattern (32) with the lead pattern (30). These two patterns (30, 32) are then transferred downward into respective conductive layers (26, 28) of the semiconductor device (10). An insulating layer (34) is deposited over the conductive layers (26, 28) and etched-back to expose a portion of the pillar (28). A conductive layer (42) is applied over the exposed pillar (28).
REFERENCES:
patent: 4799093 (1989-01-01), Kohara et al.
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 4851895 (1989-07-01), Green et al.
Barndt B. Peter
Comfort James T.
Sharp Melvin
Texas Instruments Incorporated
Wojciechowicz Edward J.
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